1. Field of the Invention
The present invention relates to a semiconductor fabricating method. More particularly, the present invention relates to an improved method of fabricating a Dynamic Random Access Memory (DRAM) capacitor.
2. Description of the Related Art
As the function of a microprocessor becomes more powerful and the amount of computation being processed by software programs increases, required memory capacity increases correspondingly. The capacitor is the heart for storing input signal in the DRAM. As the amount of charges stored in a capacitor increases, soft errors easily occur. The performance of the capacitor thus is decreased. There are three methods for increasing the storage capacity of the capacitor. (1) A dielectric layer with a high dielectric constant is used to increase the amount of charges stored in per unit area of a capacitor. (2) The thickness of a dielectric layer is reduced to obtain an increased capacitance. However, the thickness of the dielectric layer that can be reduced is limited in order to maintain the quality of the dielectric layer. (3) The surface area of a capacitor is increased to increase the amount of charges stored in a capacitor. However, as the surface area of a capacitor increases, the integration of a device decreases.
A two-dimensional planar type capacitor is used in an integrated circuit for a conventional DRAM that stores only a small amount of charge. The planar-type capacitor occupies a sizeable surface area on a substrate. Hence, the planar type capacitor is not suitable for a highly integrated DRAM. To achieve a highly integrated DRAM, a three-dimensional capacitor, such as a stacked-type or a trench-type capacitor, is adopted. However, to realize a semiconductor device of an even higher degree of integration, even a simple three-dimensional capacitor is insufficient.
FIGS. 1A through 1D are schematic, cross-sectional views showing a conventional fabricating method of a cylindrical capacitor.
In FIG. 1A. an isolation structure 101 is formed on a semiconductor substrate 100. The isolation structure 101 is used to define active regions of the semiconductor substrate 100. A DRAM transistor 103 is formed on the semiconductor substrate 100. The transistor 103 includes a gate 104 and a source/drain region 102. The source/drain region 102 is located in the semiconductor substrate 100 beside the gate 104. A dielectric layer 106 is formed over the semiconductor substrate 100. The dielectric layer 106 is patterned to form a storage node opening 108 through the dielectric layer 106 and expose the source/drain region 102.
In FIG. 1B, a first polysilicon layer 110 is formed on the dielectric layer 106 to fill the storage node opening 108. A patterned oxide layer 112 is formed on the first polysilicon layer 110. The patterned oxide layer 112 is aligned with the storage node opening 108. A second polysilicon layer 114 is formed over the semiconductor substrate 100.
In FIG. 1C, anisotropic etching is performed to remove a portion of the second polysilicon layer 114 until the dielectric layer 106 and the patterned oxide layer 112 are exposed. A polysilicon spacer 114a remaining from the second polysilicon layer 114 is formed on the sidewall of the oxide layer 112.
In FIG. 1D, wet etching is performed to remove the oxide layer 112. A storage electrode is formed. The storage electrode is composed of the first polysilicon layer 110 and the second polysilicon layer 114a. A thin dielectric layer 116 and a top electrode 118 are formed in sequence over the semiconductor substrate 100.
FIGS. 2A through 2B are schematic, cross-sectional views showing a conventional fabricating method of another cylindrical capacitor.
In FIG. 2A, an isolation structure 201 is formed in the semiconductor substrate 200. The isolation structure 201 is used to define active regions of the semiconductor substrate 200. A DRAM transistor 203 is formed on the semiconductor substrate 200. The transistor 203 includes a gate 204 and a source/drain region 202. The source/drain region is located in the semiconductor substrate 200 beside the gate 204. A dielectric layer 206 is formed over the semiconductor substrate 200. The dielectric layer 206 is patterned to form a storage node opening 208. The storage node opening 208 is formed through the dielectric layer 206 to expose the source/drain region 202. A patterned polysilicon layer 210 is formed on the dielectric layer 206. The patterned polysilicon layer 210 fills the storage node opening 208 to electrically couple with the source/drain region 202.
In FIG. 2B. a portion of the polysilicon layer 210 above the storage node opening 208 is removed by a conventional photolithography process. A polysilicon layer 210a remains from the polysilicon layer 210. A cylindrical capacitor is formed by the polysilicon layer 210a. A thin dielectric layer 212 and a top electrode 214 are formed in sequence over the semiconductor substrate 200.
However to realize a capacitor with an even higher degree of integration, the conventional capacitor of such a simple cylindrical shape is not sufficient. The surface area of the capacitor that can be increased is limited. Thus, the capacitance of the conventional capacitor is limited. Difficulty is still encountered when trying to increase the capacitance while decreasing the planar area of a capacitor. Moreover, in the conventional capacitor described by FIG. 2A and FIG. 2B, two photolithography processes have to be carried out, which makes the process more complicated.